1. Field of the Invention
The present invention relates to technology for design planning.
2. Description of the Related Art
The use of electronic design automation (EDA) tools has become commonplace for the design of high density integrated circuits. The current design flow used by many engineers includes defining a Register Transfer Level (RTL) description of the design, performing logic synthesis from the RTL to generate a netlist, placing and routing the components in the netlist, and performing verification and analysis of the placed and routed design to verify that the end result performs as intended.
Many logic synthesis tools will create a netlist in a hierarchical format. However, many placement tools require the netlist to be flat. Therefore, many design processes will utilize a tool that will flatten the hierarchical netlist. However, some designs have more components than a placement tool can reasonably handle. To overcome the restrictions regarding the number of components that can be placed by an automatic placement tool, typical design process will have human engineers manually place hard macros and then the remaining gates will be clustered based on connectivity. That is, gates that are connected together are grouped as a single object (clusters). The automatic placement tool then places the clusters around the hard macros. Note that a hard macro is a usually larger object that typically is fixed in size and shape. Hard macros typically cannot be changed. By replacing the many gates with a smaller number of clusters (groups of gates), the placement task is simplified. Subsequently, the placement tool is run within each cluster to place the gates within the clusters. Historically, when the human engineer manually places the hard macros, the hard macros are situated at the edges of the integrated circuit. For example, FIG. 1 shows an integrated circuit 10 after manual placement of hard macros 20, 22, 24 and 26. As illustrated, hard macros 20, 22, 24 and 26 are positioned near the edge/perimeter 28 of integrated circuit 10.
The problem with the above-described process is that much space on the integrated circuit is wasted due to poor placement of components. To remain competitive in a globally competitive marketplace, a maker of integrated circuits needs to be able to include as much logic on an integrated circuit as possible. Therefore, there is a need to improve the ability to place objects on an integrated circuit in a manner that more efficiently uses the available area of the integrated circuit.